The present invention relates to a semiconductor memory device; and, more particularly, to a data transfer circuit for a write operation in the semiconductor memory device.
As well-known in the art, a semiconductor memory device is a semiconductor device which stores a large amount of data and provides desired data among the stored data. The main operations of the semiconductor memory device include a write operation for storing data and a read operation for outputting selected data out of the stored data. Further, there exists a precharge operation for getting the read and write operations ready when those operations are not done. In addition, it is required that the semiconductor memory device that uses a capacitor as a data storage unit like DRAM performs a refresh operation for compensating the natural leakage of signal stored in the capacitor.
Such a semiconductor memory device is embodied in a manner that the unit cells that are the basic component for data storage are arranged in a matrix form in order to efficiently store a large amount of data. Each of the unit cells arranged in the matrix form is disposed at a point where each of word lines in a horizontal direction intersects each of bit lines in a vertical direction. Each of the word lines corresponds to a row address, while each of the bit lines corresponds to a column address. In general, in case of performing the read or write operation, a row address is first taken to select a corresponding one of the word lines. Then, a column address is received to select a corresponding one of the bit lines. The data of a unit cell designated by the selected word line and bit line denotes data to be accessed.
For more efficient structure, the semiconductor device receives both a row address and a column address through one address input pad, and shares a pad through which data is inputted or outputted. During the read operation, data is outputted through the input/output pad, and during the write operation, data is inputted through the input/output pad. For this, one data transfer path is established between the unit cell and the input/output pad. In the data transfer path, a transfer circuit for data write and a transfer circuit for data read are provided for transferring data in predetermined directions during the read and write operations.
To transfer data corresponding to a read command from a data transfer line to outside and transfer data corresponding to a write command from the outside to a data storage area via one data transfer line as above, the transfer circuits for data write and read have to accurately transfer data in preset directions in response to the corresponding commands. Further, it needs to reset the data transfer line in order to convey the data corresponding to the write command via the same after outputting the data corresponding to the read command to the outside via it. If it fails to reset the data transfer line normally, the data signal corresponding to the read command collides with the data signal corresponding to the write command on one data transfer line, which may cause an error.